In semiconductor processing, a plurality of dies, each containing an integrated circuit, are fabricated on a semiconductor wafer. Scribe lines are provided between adjacent dies so that the dies can be separated without damaging the circuit during processing. Typically, stresses induced by semiconductor back-end processes, such as die-sawing, packing, and plastic modeling, cause serious peeling and cracking starting from the die corners. Existing methods include die saw blade improvement and seal ring consolidation. However, a severe cracking resulting from back-end processing is still observed, particularly in the die corner areas. Additionally, the consolidated seal ring structure costs a portion of precious integrated circuit area inside the die.
Accordingly, what is needed is a cost-effective semiconductor structure that reduces corner peeling and eliminates cracking of the integrated circuits.